Zilog Z80

Zilog Z80 registers
	Main registers
	Alternate registers
	Index registers
IX	Index X
IY	Index Y
SP	Stack Pointer
	Other registers
	Program counter
PC	Program Counter
	Status register

Zilog Z80
General information
Launched	March 1976
Common manufacturer(s)	Zilog, Mostek, Synertek, SGS-Thomson, NEC, Sharp, Toshiba, Rohm, GoldStar (LG), Hitachi, National Semiconductor and others;
Performance
Max. CPU clock rate	2.5 MHz to 20 MHz
Data width	8 bits
Address width	16 bits
Architecture and classification
Instruction set	Z80
Physical specifications
Package(s)	40-pin DIP, 44-pin PLCC, 44-pin QFP;
Socket(s)	Not applicable;
History
Successor(s)	Z8000; Z800/Z280; Z180; Z380; eZ80;

The Zilog Z80 is an 8-bit processor that is a software-compatible extension of the Intel 8080. In addition to having a binary compatible ISA to the 8080, the processor offered many different improvements which allowed the Z80 to become the most widely used CPUs in desktop and home computers from the 1970s to the mid-1980s.

Design

Registers

There are seven 8-bit general registers (A, B, C, D, E, H and L) where A is the primary 8-bit accumulator, eight shadow registers (A', F', B', C', D', E', H' and L'), two 16-bit index registers (IX and IY), two external control registers (I, and R) and one status register. The six general registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE and HL) depending on the particular instruction. Specific instructions allow the use of accessing the lower and upper bytes of the two 16-bit index registers (as IXL, IXH, IYL and IYH respectively).

The AF' register is the only shadow register which can be used as a parameter. The AF' shadow register can only be used with the EX AF, AF' instruction. The other three remaining shadow registers can be exchanged at once using the EXX instruction.

The refresh register (R) provides the computer the capability of refreshing dynamic access memory, as it increments every fetch of an opcode or opcode prefix.

The interrupt vector register (I) is used when the interrupt mode is IM2, to set the upper 8 bits of the interrupt vector. When an interrupt is received in this mode, a byte will be passed by the interrupting device. The byte passed by the interrupting device will be combined with the interrupt vector register shifted by 8 to form the complete 16-bit address to the vector table. When interrupt modes IM0 and IM1 are used, the interrupt vector register can be used as a limited extra register.

Flags

The processor maintains an internal status register for storing bit flags representing the state of arithmetic and logic operations.

Sign (S), set if the result is negative.
Zero (Z), set if the result is zero.
Half-carry (H), used for binary-coded decimal (BCD) arithmetic.
Parity/Overflow (P/V), set if the number of bits set to 1 is even or if the operation resulted in an overflow.
Add/Subtract (N), set to distinguish between addition and subtraction during decimal adjust accumulator instructions. All additions, N = 0; all subtractions, N = 1.
Carry (C), set if the last addition operation resulted in a carry, or the last subtraction operation resulted in a borrow.

Input/Output control

The Z80 supports up to 256 independent I/O ports, accessed through dedicated I/O instructions taking port addresses as operands.

Pinouts

Pin number	Signal	Type	Comment
1	A11	Output	Address bus [11..15], Trisate
2	A12
3	A13
4	A14
5	A15
6	CLK	Input	Clock
7	D4	Bidirectional	Data bus [3..6], Tristate
8	D3
9	D5
10	D6
11	V_CC	—	+5V power supply
12	D2	Bidirectional	Data bus [0..2, 7], Tristate
13	D7
14	D0
15	D1
16	INT	Input	Interrupt request
17	NMI	Input	Non-maskable interrupt request
18	HALT	Output	Halt. Indicates the processor is stopped. A signal on RESET is required to resume
19	MREQ		Memory request. Indicates the processor is requesting or writing data from/to a memory address
20	IORQ		Input/Output request. Indicates the processor is requesting or writing data from/to am I/O port
21	RD		Read. Indicates the processor is reading data
22	WR		Write. Indicates the processor is writing data
23	BUSACK		Bus Acknowledge. Indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ, RD and WR have entered their high-impedance state. The external circuitry can now control these lines
24	WAIT	Input	Wait. This introduces wait-states in to the current machine cycle for as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory
25	BUSRQ		Bus request. Has a high priority than NMI and is always recognized at the end of the current machine cycle. Forces the CPU address bus, data bus, and control signals MREQ, IORQ, RD and WR to enter their high-impedance state
26	RESET		Reset. Initializes the CPU as follows: it resets the interrupt flip-flop, clears the Program Counter (PC) and registers I and R, and sets the interrupt mode to 0. During reset time, the address and data busses enter a high-impedance state, and all control output signals enter an inactive state. RESET must be active for a minimum of three full clock cycles before a reset operation is complete
27	M1	Output	Machine Cycle One. M1 combined with MREQ, indicates that the current machine cycle is the op code fetch cycle of an instruction execution. M1 combined with IORQ, indicates an interrupt acknowledge cycle
28	RFSH	Output	Refresh. RFSH combined with MREQ, indicates that the lower seven bits of the address bus can be used as a refresh address for dynamic memory
29	GND	—	Ground
30	A0	Output	Address bus [0..10], Tristate
31	A1
32	A2
33	A3
34	A4
35	A5
36	A6
37	A7
38	A8
39	A9
40	A10

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