Zilog eZ80
| General information | |
|---|---|
| Launched | 2001 |
| Common manufacturer(s) | |
| Performance | |
| Max. CPU clock rate | to 50 MHz |
| Data width | 8 bits |
| Address width | 16 bits in Z80 mode, 24 bits in ADL mode |
| Virtual address width | 24 bits |
| Architecture and classification | |
| Instruction set | Z80 |
| History | |
| Predecessor(s) | |
The Zilog eZ80 is an 8-bit processor that is the successor to the Z80 line of products from Zilog. It is binary compatible with the previous generation of processors, but almost three times as fast as its predecessors due to the addition of a three-stage pipeline (fetch, decode and execute).
Design
Registers
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The eZ80 expands upon the Z80 series processor designs by increasing the size of the general registers from 16 to 24 bits in length. This allows the processor to address up to 16 MB of memory without the requirement of a memory management unit.
There are seven 8-bit general registers (A, B, C, D, E, H and L), where A is the primary 8-bit accumulator, eight shadow registers (A', F', B', C', D', E', H' and L'), two 16-bit index registers (IX and IY), three external control registers (I, MBASE and R) and one status register. The six general registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE and HL) depending on the particular instruction. Specific instructions allow the use of accessing the lower and upper bytes of the two 16-bit index registers (as IXL, IXH, IYL and IYH respectively).
The AF' register is the only shadow register which can be used as a parameter. The AF' shadow register can only be used with the EX AF, AF' instruction. The other three remaining shadow registers can be exchanged at once using the EXX instruction.
The refresh register (R) provides the computer the capability of refreshing dynamic access memory, as it increments every fetch of an opcode or opcode prefix.
The interrupt vector register (I) is used when the interrupt mode is IM2, to set the upper 16 bits of the interrupt vector. When an interrupt is received in this mode, a byte will be passed by the interrupting device. The byte passed by the interrupting device will be combined with the interrupt vector register shifted by 8 to form the complete 24-bit address to the vector table. When interrupt modes IM0 and IM1 are used, the interrupt vector register can be used as a limited extra register.
The memory base register (MBASE) is a 8-bit special register that determines the current page of memory when the processor is in Z80 mode. It cannot be written to except when in ADL mode. The MBASE register is added to the upper 8 bits with the lower 15 bits of the program counter to form the full 24-bit address when in Z80 mode.
24-bit extensions
When utilizing the ADL addressing mode, the three general register pairs and two index registers become 24 bits in length, and the far upper 8 bits can be identified through their new extension names (BCU, DEU, HLU, IXU and IYU respectively). The extension also applies to the three shadow register pairs (BCU', DEU' and HLU'). Meanwhile, the far upper byte of these registers are not individually accessible as standalone registers.
The stack pointer short (SPS) becomes stack pointer long (SPL), but the program counter (PC) doesn't change. Both of these registers also change to be 24 bits in length as well.