Intel 8080

Intel 8080

General information
Launched	April 1974
Common manufacturer(s)	Intel
Performance
Max. CPU clock rate	2 MHz to 3.125 MHz
Data width	8 bits
Address width	16 bits
Architecture and classification
Instruction set	8080
History
Predecessor(s)	Intel 8008
Successor(s)	Intel 8085

The Intel 8080 is an 8-bit processor and successor of the Intel 8008.

Design

While the 8080 uses the same basic instruction set and register model as the 8008, it is neither source nor binary compatible with its predecessor. The 8080 adds 16-bit operations to its instruction set. Additionally, unlike the 8008's restriction of only being able to use a 14-bit memory space indirectly through the HL register, the 8080 allows to use the full 16-bit address space.

Power requirements

The 8080 has a power supply scheme common with integrated circuits of the era, requiring both a +5V and a -5V rail in addition to a +12V rail. The 8080 has very strict power up and power down conditions that must be observed in order to prevent damage to the chip. Upon power up, the -5V rail must be connected first, then the +5V rail and finally the +12V rail, and on power down the reverse (+12V → +5V → -5V).

Registers

Intel 8080 registers

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

(bit position)

Main registers

A

Flags

Program Status Word

B

C

B

D

E

D

H

L

H (indirect address)

Index registers

SP

Stack Pointer

Program counter

PC

Program Counter

Status register

S

Z

–

AC

–

P

–

C

Flags

There are seven 8-bit general registers (A, B, C, D, E, H and L) and one status register, where A is the primary 8-bit accumulator. The other six registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE and HL, referred to as B, C and H in Intel documentation) depending on the particular instruction. Some instructions also enable the HL register pair to be used as a (limited) 16-bit accumulator. A pseudo-register M, which refers to the dereference memory location pointed to by HL, can be used almost anywhere other registers can be used. The 8080 has a 16-bit stack pointer (SP) to memory, replacing the 8008's internal stack, and a 16-bit program counter (PC).

Flags

The processor maintains an internal status register for storing bit flags representing the state of arithmetic and logic operations.

• Sign (S), set if the result is negative.
• Zero (Z), set if the result is zero.
• Parity (P), set if the number of bits set to 1 is even.
• Carry (C), set if the last addition operation resulted in a carry, or the last subtraction operation resulted in a borrow.
• Auxiliary carry (AC or H), used for binary-coded decimal (BCD) arithmetic.

Input/Output control

The 8080 supports up to 256 independent I/O ports, accessed through dedicated I/O instructions taking port addresses as operands.

Pinouts

Pin number	Signal	Type	Comment
1	A10	Output	Address bus 10
2	GND	—	Ground
3	D4	Bidirectional	Bidirectional data bus. The processor also transiently sets here the "processor state", providing information about what the processor is currently doing: D0 reading interrupt command. In response to the interrupt signal, the processor is reading and executing a single arbitrary command with this flag raised. Normally the supporting chips provide the subroutine call command (CALL or RST), transferring control to the interrupt handling code. D1 reading (low level means writing) D2 accessing stack (probably a separate stack memory space was initially planned) D3 doing nothing, has been halted by the HLT instruction D4 writing data to an output port D5 reading the first byte of an executable instruction D6 reading data from an input port D7 reading data from memory
4	D5
5	D6
6	D7
7	D3
8	D2
9	D1
10	D0
11	−5 V	—	The −5 V power supply. This must be the first power source connected and the last disconnected, otherwise the processor will be damaged.
12	RESET	Input	Reset. The signal forces execution of commands located at address 0000. The content of other processor registers is not modified. This is an inverting input (the active level being logical 0)
13	HOLD	Input	Direct memory access request. The processor is requested to switch the data and address bus to the high impedance ("disconnected") state.
14	INT	Input	Interrupt request
15	φ2	Input	The second phase of the clock generator signal
16	INTE	Output	The processor has two commands for setting 0 or 1 level on this pin. The pin normally is supposed to be used for interrupt control. However, in simple computers it was sometimes used as a single bit output port for various purposes.
17	DBIN	Output	Read (the processor reads from memory or input port)
18	WR	Output	Write (the processor writes to memory or output port). This is an inverted output, the active level being logical zero.
19	SYNC	Output	Active level indicates that the processor has put the "state word" on the data bus. The various bits of this state word provide added information to support the separate address and memory spaces, interrupts, and direct memory access. This signal is required to pass through additional logic before it can be used to write the processor state word from the data bus into some external register, e.g., 8238-System Controller and Bus Driver.
20	+5 V	—	The + 5 V power supply
21	HLDA	Output	Direct memory access confirmation. The processor switches data and address pins into the high impedance state, allowing another device to manipulate the bus
22	φ1	Input	The first phase of the clock generator signal
23	READY	Input	Wait. With this signal it is possible to suspend the processor's work. It is also used to support the hardware-based step-by step debugging mode.
24	WAIT	Output	Wait (indicates that the processor is in the waiting state)
25	A0	Output	Address bus
26	A1
27	A2
28	12 V	—	The +12 V power supply. This must be the last connected and first disconnected power source.
29	A3	Output	The address bus; can switch into high impedance state on demand
30	A4
31	A5
32	A6
33	A7
34	A8
35	A9
36	A15
37	A12
38	A13
39	A14
40	A11