Zilog Z80

Zilog Z80

General information
Launched	March 1976
Designed by	Federico Faggin, Masatoshi Shima
Common manufacturer(s)	Mostek, Synertek, Zilog, SGS-Thomson, NEC, Sharp, Toshiba, Rohm, GoldStar (LG), Hitachi, National Semiconductor and others
Performance
Max. CPU clock rate	2.5, 4, 6, 8 MHz to 10 MHz with CMOS variant up to 20 MHz and binary compatible derivatives (from Zilog) up to 33 and 50 MHz
Data width	8 bits
Address width	16 bits
Architecture and classification
Instruction set	Z80
Physical specifications
Transistors	8500 (4 μm process)
Package(s)	40-pin DIP, 44-pin PLCC, 44-pin QFP
Socket(s)	Not applicable
History
Predecessor(s)	Intel 8080
Successor(s)	Z8000 Z800/Z280 Z180 Z380 eZ80

The Zilog Z80 is an 8-bit processor that is a software-compatible extension of the Intel 8080. In addition to having a binary compatible ISA to the 8080, the processor offered many different improvements which allowed the Z80 to become the most widely used CPUs in desktop and home computers from the 1970s to the mid-1980s.

Design

Registers

Zilog Z80 registers

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers A Flags AF (8 bit accumulator and flags) B C BC (data and address register) D E DE (data and address register) H L HL (16 bit accumulator and address register) Alternate registers A' Flags' AF' (8 bit accumulator and flags) B' C' BC' (data and address register) D' E' DE' (data and address register) H' L' HL' (16 bit accumulator and address register) Index registers IX Index X IY Index Y SP Stack Pointer Other registers   I Interrupt vector   R Refresh counter Program counter PC Program Counter Status register   S Z - H - P/V N C Flags

As on the 8080, 8-bit registers are typically paired to provide 16-bit versions. The 8080 compatible registers are:

• AF: 8-bit accumulator (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used for BCD), and an Add/Subtract flag (usually called N) also for BCD
• BC: 16-bit data/address register or two 8-bit registers
• DE: 16-bit data/address register or two 8-bit registers
• HL: 16-bit accumulator/address register or two 8-bit registers
• SP: stack pointer, 16 bits
• PC: program counter, 16 bits

The new registers introduced with the Z80 are:

• IX: 16-bit index or base register for 8-bit immediate offsets
• IY: 16-bit index or base register for 8-bit immediate offsets
• I: interrupt vector base register, 8 bits
• R: DRAM refresh counter, 8 bits (msb does not count)
• AF': alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF' )
• BC', DE' and HL': alternate (or shadow) registers (toggled in and out with EXX)
• Four bits of interrupt status and interrupt mode status

The refresh register, R, increments each time the CPU fetches an opcode (or an opcode prefix, which internally executes like a 1-byte instruction) and has no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes.Template:Citation needed It has also been employed as a "hardware" counter in some designs; an example of this is the ZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6).

The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via an index sent to the CPU during an interrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine. The pointer identifies a particular peripheral chip or peripheral function or event, where the chips are normally connected in a so-called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in a system not using interrupts) it can be used as simply another 8-bit data register.