Zilog Z80: Difference between revisions

From Fox Labs Wiki
Jump to navigation Jump to search
Line 135: Line 135:


The [[interrupt vector register]] ('''I''') is used when the interrupt mode is IM2, to set the upper 8 bits of the [[interrupt vector]]. When an interrupt is received in this mode, a byte will be passed by the interrupting device. The byte passed by the interrupting device will be combined with the interrupt vector register shifted by 8 to form the complete 16-bit address to the vector table. When interrupt modes IM0 and IM1 are used, the interrupt vector register can be used as a limited extra register.
The [[interrupt vector register]] ('''I''') is used when the interrupt mode is IM2, to set the upper 8 bits of the [[interrupt vector]]. When an interrupt is received in this mode, a byte will be passed by the interrupting device. The byte passed by the interrupting device will be combined with the interrupt vector register shifted by 8 to form the complete 16-bit address to the vector table. When interrupt modes IM0 and IM1 are used, the interrupt vector register can be used as a limited extra register.
==== Flags ====
The processor maintains an internal [[status register]] for storing [[Flag word|bit flags]] representing the state of arithmetic and logic operations.
* [[Sign flag|Sign]] (S), set if the result is negative.
* [[Zero flag|Zero]] (Z), set if the result is zero.
* [[Auxiliary carry flag|Half-carry]] (H), used for [[binary-coded decimal]] (BCD) arithmetic.
* [[Parity flag|Parity]]/[[Overflow flag|Overflow]] (P/V), set if the number of bits set to 1 is even or if the operation resulted in an overflow.
* Add/Subtract (N), set to distinguish between addition and subtraction during decimal adjust accumulator instructions. All additions, N = 0; all subtractions, N = 1.
* [[Carry flag|Carry]] (C), set if the last addition operation resulted in a carry, or the last subtraction operation resulted in a borrow.
=== Input/Output control ===
The Z80 supports up to 256 independent I/O ports, accessed through dedicated I/O instructions taking port addresses as operands.
[[Category:Zilog Microprocessors]]
[[Category:Zilog Microprocessors]]
[[Category:8-bit microprocessors]]
[[Category:8-bit microprocessors]]

Revision as of 01:00, 5 November 2023

Zilog Z80
General information
LaunchedMarch 1976
Common manufacturer(s)
Performance
Max. CPU clock rate2.5 MHz to 20 MHz
Data width8 bits
Address width16 bits
Architecture and classification
Instruction setZ80
Physical specifications
Package(s)
Socket(s)
  • Not applicable
History
Predecessor(s)
Successor(s)

The Zilog Z80 is an 8-bit processor that is a software-compatible extension of the Intel 8080. In addition to having a binary compatible ISA to the 8080, the processor offered many different improvements which allowed the Z80 to become the most widely used CPUs in desktop and home computers from the 1970s to the mid-1980s.

Design

Registers

Zilog Z80 registers
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
Main registers
A Flags AF (8 bit accumulator and flags)
B C BC (data and address register)
D E DE (data and address register)
H L HL (16 bit accumulator and address register)
Alternate registers
A' Flags' AF' (8 bit accumulator and flags)
B' C' BC' (data and address register)
D' E' DE' (data and address register)
H' L' HL' (16 bit accumulator and address register)
Index registers
IX Index X
IY Index Y
SP Stack Pointer
Other registers
  I Interrupt vector
  R Refresh counter
Program counter
PC Program Counter
Status register
  S Z - H - P/V N C Flags

There are seven 8-bit general registers (A, B, C, D, E, H and L) where A is the primary 8-bit accumulator, eight shadow registers (A', F', B', C', D', E', H' and L'), two 16-bit index registers (IX and IY), two external control registers (I, and R) and one status register. The six general registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE and HL) depending on the particular instruction. Specific instructions allow the use of accessing the lower and upper bytes of the two 16-bit index registers (as IXL, IXH, IYL and IYH respectively).

The AF' register is the only shadow register which can be used as a parameter. The AF' shadow register can only be used with the EX AF, AF' instruction. The other three remaining shadow registers can be exchanged at once using the EXX instruction.

The refresh register (R) provides the computer the capability of refreshing dynamic access memory, as it increments every fetch of an opcode or opcode prefix.

The interrupt vector register (I) is used when the interrupt mode is IM2, to set the upper 8 bits of the interrupt vector. When an interrupt is received in this mode, a byte will be passed by the interrupting device. The byte passed by the interrupting device will be combined with the interrupt vector register shifted by 8 to form the complete 16-bit address to the vector table. When interrupt modes IM0 and IM1 are used, the interrupt vector register can be used as a limited extra register.

Flags

The processor maintains an internal status register for storing bit flags representing the state of arithmetic and logic operations.

  • Sign (S), set if the result is negative.
  • Zero (Z), set if the result is zero.
  • Half-carry (H), used for binary-coded decimal (BCD) arithmetic.
  • Parity/Overflow (P/V), set if the number of bits set to 1 is even or if the operation resulted in an overflow.
  • Add/Subtract (N), set to distinguish between addition and subtraction during decimal adjust accumulator instructions. All additions, N = 0; all subtractions, N = 1.
  • Carry (C), set if the last addition operation resulted in a carry, or the last subtraction operation resulted in a borrow.

Input/Output control

The Z80 supports up to 256 independent I/O ports, accessed through dedicated I/O instructions taking port addresses as operands.