Zilog Z80

Zilog Z80

General information
Launched	March 1976
Common manufacturer(s)	Mostek, Synertek, Zilog, SGS-Thomson, NEC, Sharp, Toshiba, Rohm, GoldStar (LG), Hitachi, National Semiconductor and others
Performance
Max. CPU clock rate	2.5 MHz to 20 MHz
Data width	8 bits
Address width	16 bits
Architecture and classification
Instruction set	Z80
Physical specifications
Package(s)	40-pin DIP, 44-pin PLCC, 44-pin QFP
Socket(s)	Not applicable
History
Predecessor(s)	Intel 8080
Successor(s)	Z8000 Z800/Z280 Z180 Z380 eZ80

The Zilog Z80 is an 8-bit processor that is a software-compatible extension of the Intel 8080. In addition to having a binary compatible ISA to the 8080, the processor offered many different improvements which allowed the Z80 to become the most widely used CPUs in desktop and home computers from the 1970s to the mid-1980s.

Design

Registers

Zilog Z80 registers

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers A Flags AF (8 bit accumulator and flags) B C BC (data and address register) D E DE (data and address register) H L HL (16 bit accumulator and address register) Alternate registers A' Flags' AF' (8 bit accumulator and flags) B' C' BC' (data and address register) D' E' DE' (data and address register) H' L' HL' (16 bit accumulator and address register) Index registers IX Index X IY Index Y SP Stack Pointer Other registers   I Interrupt vector   R Refresh counter Program counter PC Program Counter Status register   S Z - H - P/V N C Flags

There are seven 8-bit general registers (A, B, C, D, E, H and L) where A is the primary 8-bit accumulator, eight shadow registers (A', F', B', C', D', E', H' and L'), two 16-bit index registers (IX and IY), two external control registers (I, and R) and one status register. The six general registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE and HL) depending on the particular instruction. Specific instructions allow the use of accessing the lower and upper bytes of the two 16-bit index registers (as IXL, IXH, IYL and IYH respectively).

The AF' register is the only shadow register which can be used as a parameter. The AF' shadow register can only be used with the EX AF, AF' instruction. The other three remaining shadow registers can be exchanged at once using the EXX instruction.

The refresh register (R) provides the computer the capability of refreshing dynamic access memory, as it increments every fetch of an opcode or opcode prefix.

The interrupt vector register (I) is used when the interrupt mode is IM2, to set the upper 8 bits of the interrupt vector. When an interrupt is received in this mode, a byte will be passed by the interrupting device, and that will be expressed on the address bus as the lower 8 bits and the I register value combined to form the interrupt vector during the acknowledge-fetch cycle. When interrupt modes IM0 and IM1 are used, the interrupt vector register can be used as a limited extra register.