The Zilog Z80 instruction set is a simple set of instructions. There are several extensions which provides an extended set of instructions, some of which are only available on the Z180 and newer or may be undocumented instructions introduced by other manufacturers than Zilog.
Identifies any of the registers A, B, C, D, E, H or L
(HL)
Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL.
(IX+d)
Identifies the contents of the memory location, whose address is specified by the contents of the Index Register IX plus the signed displacement d.
(IY+d)
Identifies the contents of the memory location, whose address is specified by the contents of the Index Register IY plus the signed displacement d.
n
Identifies a one-byte unsigned integer (0 to 255).
nn
Identifies a two-byte unsigned integer (0 to 65535).
d
Identifies a one-byte signed integer (-128 to 127).
b
Identifies a one-bit expression in the range 0 to 7. The most-significant bit position (left-most) is bit 7, and the least-significant bit position (right-most) is bit 0.
e
Identifies a one-byte signed integer (-126 to 129) for relative jump offset from the current address.
cc
Identifies the status register flag as any of NZ, Z, NC, C, PO, PE, P or M, for conditional jumps, calls and return instructions.
qq
Identifies any of the register pairs BC, DE, HL or AF.
ss
Identifies any of the register pairs BC, DE, HL or the stack pointer SP.
pp
Identifies any of the register pairs BC, DE, the Index Register IX or the Stack Pointer (SP).
rr
Identifies any of the register pairs BC, DE, the Index Register IY or the Stack Pointer (SP).
s
Identifies any of r, n, (HL), (IX+d), (IY+d).
m
Identifies any of r, (HL), (IX+d), (IY+d).
8-bit Load Instructions
LD r, r'
7
6
5
4
3
2
1
0
0
1
← r →
← r' →
The contents of any register r' is loaded to any other register r. r, r' identifies any of the registers A, B, C, D, E, H or L, as follows:
A
B
C
D
E
H
L
111
000
001
010
011
100
101
Flags affected
None.
LD r, n
7
6
5
4
3
2
1
0
0
0
← r →
1
1
0
← n →
The 8-bit integer n is loaded in to any register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:
A
B
C
D
E
H
L
111
000
001
010
011
100
101
Flags affected
None.
LD r, (HL)
7
6
5
4
3
2
1
0
0
1
← r →
1
1
0
The 8-bit contents of the memory location HL is loaded in to register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:
A
B
C
D
E
H
L
111
000
001
010
011
100
101
Flags affected
None.
LD r, (IX+d)
7
6
5
4
3
2
1
0
1
1
0
1
1
1
0
1
DD
0
1
← r →
1
1
0
← d →
The (IX+d) operand (ie: the contents of Index Register IX summed with the two's complement displacement integer d) is loaded in to register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:
A
B
C
D
E
H
L
111
000
001
010
011
100
101
Flags affected
None.
LD r, (IY+d)
7
6
5
4
3
2
1
0
1
1
1
1
1
1
0
1
FD
0
1
← r →
1
1
0
← d →
The (IY+d) operand (ie: the contents of Index Register IY summed with the two's complement displacement integer d) is loaded in to register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:
A
B
C
D
E
H
L
111
000
001
010
011
100
101
Flags affected
None.
LD (HL), r
7
6
5
4
3
2
1
0
0
1
1
1
0
← r →
The contents of the register r is loaded in to the memory location HL, in which r identifies any of the registers A, B, C, D, E, H or L, as follows: