Logic gate: Difference between revisions
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| {{yes2|1}} || {{no2|0}} | | {{yes2|1}} || {{no2|0}} | ||
|} | |} | ||
|- | |- | ||
|[[AND gate]] | |[[AND gate]] | ||
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|<math>A \cdot B</math> or <math>A \land B</math> | |<math>A \cdot B</math> or <math>A \land B</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input''' || '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{no2|0}} | |||
|- " | |||
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}} | |||
|} | |||
|- | |- | ||
|[[OR gate]] | |[[OR gate]] | ||
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|<math>A + B</math> or <math>A \lor B</math> | |<math>A + B</math> or <math>A \lor B</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input'''|| '''Output''' | |||
|- style="background:#def" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{yes2|1}} | |||
|- | |- | ||
| | | {{yes2|1}} || {{no2|0}} || {{yes2|1}} | ||
| | |- | ||
| | | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} | ||
| | |} | ||
|- | |- | ||
|[[NAND gate]] | |[[NAND gate]] | ||
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|<math>\overline { A \cdot B }</math> or <math>\neg(A \land B)</math> | |<math>\overline { A \cdot B }</math> or <math>\neg(A \land B)</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input'''|| '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{yes2|1}} || {{no2|0}} | |||
|} | |||
|- | |- | ||
|[[NOR gate]] | |[[NOR gate]] | ||
Line 73: | Line 108: | ||
|<math>\overline { A + B }</math> or <math>\neg(A \lor B)</math> | |<math>\overline { A + B }</math> or <math>\neg(A \lor B)</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input''' || '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{no2|0}} | |||
|- | |- | ||
| | | {{yes2|1}} || {{yes2|1}} || {{no2|0}} | ||
| | |} | ||
| | |||
| | |||
|- | |- | ||
|[[XOR gate]] | |[[XOR gate]] | ||
Line 83: | Line 128: | ||
|<math>A \oplus B</math> or <math>A \underline \lor B</math> | |<math>A \oplus B</math> or <math>A \underline \lor B</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input'''|| '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{yes2|1}} || {{no2|0}} | |||
|} | |||
|- | |- | ||
|[[XNOR gate]] | |[[XNOR gate]] | ||
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|<math>\overline { A \oplus B }</math> or <math>A \odot B</math> | |<math>\overline { A \oplus B }</math> or <math>A \odot B</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input'''|| '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}} | |||
|} | |||
|} | |} | ||
{{Stub}} | {{Stub}} | ||
= See also = | |||
* [[Combinational logic]] | |||
* [[List of 4000 series integrated circuits]] | |||
* [[List of 7400 series integrated circuits]] | |||
* [[Logic level]] | |||
{{Digital systems}} | |||
[[Category:Logic gates]] | [[Category:Logic gates]] |
Revision as of 14:47, 9 November 2023
A logic gate is an idealized or physical device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output.
Symbols
Type | ANSI symbol | Boolean algebra | Truth table | ||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Single-input gates | |||||||||||||||||||||
Buffer | ![]() |
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Inverter | ![]() |
or |
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AND gate | ![]() |
or |
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OR gate | ![]() |
or |
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NAND gate | ![]() |
or |
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NOR gate | ![]() |
or |
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XOR gate | ![]() |
or |
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XNOR gate | ![]() |
or |
|