Zilog Z80 instruction set: Difference between revisions
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(Created page with "The '''Zilog Z80 instruction set''' is a simple set of instructions. There are several extensions which provides an extended set of instructions, some of which are only available on the Z180 and newer or may be undocumented instructions introduced by other manufacturers than Zilog. {{Table alignment}} {| class="wikitable defaultcenter" |+Z80 base instruction table ! !0 !1 !2 !3 !4 !5 !6 !7 !8 !9 !A !B !C !D !E !F |- |{{Rh}}|0 |nop |ld bc,''nn'' |ld (bc),a |inc bc |i...") |
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|inc b | |inc b | ||
|dec b | |dec b | ||
|ld b,''n'' | |[[Zilog Z80 instruction set#ld-rn|ld b,''n'']] | ||
|rlca | |rlca | ||
|ex af,af' | |ex af,af' | ||
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|inc c | |inc c | ||
|dec c | |dec c | ||
|ld c,''n'' | |[[Zilog Z80 instruction set#ld-rn|ld c,''n'']] | ||
|rrca | |rrca | ||
|- | |- | ||
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|inc d | |inc d | ||
|dec d | |dec d | ||
|ld d,''n'' | |[[Zilog Z80 instruction set#ld-rn|ld d,''n'']] | ||
|rla | |rla | ||
|jr d | |jr d | ||
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|inc e | |inc e | ||
|dec e | |dec e | ||
|ld e,''n'' | |[[Zilog Z80 instruction set#ld-rn|ld e,''n'']] | ||
|rra | |rra | ||
|- | |- | ||
Line 65: | Line 65: | ||
|inc h | |inc h | ||
|dec h | |dec h | ||
|ld h,''n'' | |[[Zilog Z80 instruction set#ld-rn|ld h,''n'']] | ||
|daa | |daa | ||
|jr z,d | |jr z,d | ||
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|inc l | |inc l | ||
|dec l | |dec l | ||
|ld l,''n'' | |[[Zilog Z80 instruction set#ld-rn|ld l,''n'']] | ||
|cpl | |cpl | ||
|- | |- | ||
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|inc a | |inc a | ||
|dec a | |dec a | ||
|ld a,''n'' | |[[Zilog Z80 instruction set#ld-rn|ld a,''n'']] | ||
|ccf | |ccf | ||
|- | |- | ||
|{{Rh}}|4 | |{{Rh}}|4 | ||
|ld b,b | |[[Zilog Z80 instruction set#ld-rr|ld b,b]] | ||
|ld b,c | |[[Zilog Z80 instruction set#ld-rr|ld b,c]] | ||
|ld b,d | |[[Zilog Z80 instruction set#ld-rr|ld b,d]] | ||
|ld b,e | |[[Zilog Z80 instruction set#ld-rr|ld b,e]] | ||
|ld b,h | |[[Zilog Z80 instruction set#ld-rr|ld b,h]] | ||
|ld b,l | |[[Zilog Z80 instruction set#ld-rr|ld b,l]] | ||
|ld b,(hl) | |[[Zilog Z80 instruction set#ld-rhl|ld b,(hl)]] | ||
|ld b,a | |[[Zilog Z80 instruction set#ld-rr|ld b,a]] | ||
|ld c,b | |[[Zilog Z80 instruction set#ld-rr|ld c,b]] | ||
|ld c,c | |[[Zilog Z80 instruction set#ld-rr|ld c,c]] | ||
|ld c,d | |[[Zilog Z80 instruction set#ld-rr|ld c,d]] | ||
|ld c,e | |[[Zilog Z80 instruction set#ld-rr|ld c,e]] | ||
|ld c,h | |[[Zilog Z80 instruction set#ld-rr|ld c,h]] | ||
|ld c,l | |[[Zilog Z80 instruction set#ld-rr|ld c,l]] | ||
|ld c,(hl) | |[[Zilog Z80 instruction set#ld-rhl|ld c,(hl)]] | ||
|ld c,a | |[[Zilog Z80 instruction set#ld-rr|ld c,a]] | ||
|- | |- | ||
|{{Rh}}|5 | |{{Rh}}|5 | ||
|ld d,b | |[[Zilog Z80 instruction set#ld-rr|ld d,b]] | ||
|ld d,c | |[[Zilog Z80 instruction set#ld-rr|ld d,c]] | ||
|ld d,d | |[[Zilog Z80 instruction set#ld-rr|ld d,d]] | ||
|ld d,e | |[[Zilog Z80 instruction set#ld-rr|ld d,e]] | ||
|ld d,h | |[[Zilog Z80 instruction set#ld-rr|ld d,h]] | ||
|ld d,l | |[[Zilog Z80 instruction set#ld-rr|ld d,l]] | ||
|ld d,(hl) | |[[Zilog Z80 instruction set#ld-rhl|ld d,(hl)]] | ||
|ld d,a | |[[Zilog Z80 instruction set#ld-rr|ld d,a]] | ||
|ld e,b | |[[Zilog Z80 instruction set#ld-rr|ld e,b]] | ||
|ld e,c | |[[Zilog Z80 instruction set#ld-rr|ld e,c]] | ||
|ld e,d | |[[Zilog Z80 instruction set#ld-rr|ld e,d]] | ||
|ld e,e | |[[Zilog Z80 instruction set#ld-rr|ld e,e]] | ||
|ld e,h | |[[Zilog Z80 instruction set#ld-rr|ld e,h]] | ||
|ld e,l | |[[Zilog Z80 instruction set#ld-rr|ld e,l]] | ||
|ld e,(hl) | |[[Zilog Z80 instruction set#ld-rhl|ld e,(hl)]] | ||
|ld e,a | |[[Zilog Z80 instruction set#ld-rr|ld e,a]] | ||
|- | |- | ||
|{{Rh}}|6 | |{{Rh}}|6 | ||
|ld h,b | |[[Zilog Z80 instruction set#ld-rr|ld h,b]] | ||
|ld h,c | |[[Zilog Z80 instruction set#ld-rr|ld h,c]] | ||
|ld h,d | |[[Zilog Z80 instruction set#ld-rr|ld h,d]] | ||
|ld h,e | |[[Zilog Z80 instruction set#ld-rr|ld h,e]] | ||
|ld h,h | |[[Zilog Z80 instruction set#ld-rr|ld h,h]] | ||
|ld h,l | |[[Zilog Z80 instruction set#ld-rr|ld h,l]] | ||
|ld h,(hl) | |[[Zilog Z80 instruction set#ld-rhl|ld h,(hl)]] | ||
|ld h,a | |[[Zilog Z80 instruction set#ld-rr|ld h,a]] | ||
|ld l,b | |[[Zilog Z80 instruction set#ld-rr|ld l,b]] | ||
|ld l,c | |[[Zilog Z80 instruction set#ld-rr|ld l,c]] | ||
|ld l,d | |[[Zilog Z80 instruction set#ld-rr|ld l,d]] | ||
|ld l,e | |[[Zilog Z80 instruction set#ld-rr|ld l,e]] | ||
|ld l,h | |[[Zilog Z80 instruction set#ld-rr|ld l,h]] | ||
|ld l,l | |[[Zilog Z80 instruction set#ld-rr|ld l,l]] | ||
|ld l,(hl) | |[[Zilog Z80 instruction set#ld-rhl|ld l,(hl)]] | ||
|ld l,a | |[[Zilog Z80 instruction set#ld-rr|ld l,a]] | ||
|- | |- | ||
|{{Rh}}|7 | |{{Rh}}|7 | ||
|ld (hl),b | |[[Zilog Z80 instruction set#ld-hlr|ld (hl),b]] | ||
|ld (hl),c | |[[Zilog Z80 instruction set#ld-hlr|ld (hl),c]] | ||
|ld (hl),d | |[[Zilog Z80 instruction set#ld-hlr|ld (hl),d]] | ||
|ld (hl),e | |[[Zilog Z80 instruction set#ld-hlr|ld (hl),e]] | ||
|ld (hl),h | |[[Zilog Z80 instruction set#ld-hlr|ld (hl),h]] | ||
|ld (hl),l | |[[Zilog Z80 instruction set#ld-hlr|ld (hl),l]] | ||
|halt | |halt | ||
|ld (hl),a | |[[Zilog Z80 instruction set#ld-hlr|ld (hl),a]] | ||
|ld a,b | |[[Zilog Z80 instruction set#ld-rr|ld a,b]] | ||
|ld a,c | |[[Zilog Z80 instruction set#ld-rr|ld a,c]] | ||
|ld a,d | |[[Zilog Z80 instruction set#ld-rr|ld a,d]] | ||
|ld a,e | |[[Zilog Z80 instruction set#ld-rr|ld a,e]] | ||
|ld a,h | |[[Zilog Z80 instruction set#ld-rr|ld a,h]] | ||
|ld a,l | |[[Zilog Z80 instruction set#ld-rr|ld a,l]] | ||
|ld a,(hl) | |[[Zilog Z80 instruction set#ld-rhl|ld a,(hl)]] | ||
|ld a,a | |[[Zilog Z80 instruction set#ld-rr|ld a,a]] | ||
|- | |- | ||
|{{Rh}}|8 | |{{Rh}}|8 | ||
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=== 8-bit Load Instructions === | === 8-bit Load Instructions === | ||
==== LD ''r'', ''r''' ==== | ==== LD ''r'', ''r''' {{Anchor|ld-rr}} ==== | ||
{{Table alignment}} | {{Table alignment}} | ||
{| class="wikitable defaultcenter" | {| class="wikitable defaultcenter" | ||
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None. | None. | ||
==== LD ''r'', ''n'' ==== | ==== LD ''r'', ''n'' {{Anchor|ld-rn}} ==== | ||
{{Table alignment}} | {{Table alignment}} | ||
{| class="wikitable defaultcenter" | {| class="wikitable defaultcenter" | ||
Line 379: | Line 379: | ||
|} | |} | ||
The 8-bit integer ''n'' is loaded in to any register ''r'', in which ''r'' identifies any of the registers A, B, C, D, E, H or L, as follows: | The 8-bit integer ''n'' is loaded in to any register ''r'', in which ''r'' identifies any of the registers A, B, C, D, E, H or L, as follows: | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
!A | |||
!B | |||
!C | |||
!D | |||
!E | |||
!H | |||
!L | |||
|- | |||
|111 | |||
|000 | |||
|001 | |||
|010 | |||
|011 | |||
|100 | |||
|101 | |||
|} | |||
===== Flags affected ===== | |||
None. | |||
==== LD ''r'', ''(HL)''{{Anchor|ld-rhl}} ==== | |||
{| class="wikitable defaultcenter" | |||
!7 | |||
!6 | |||
!5 | |||
!4 | |||
!3 | |||
!2 | |||
!1 | |||
!0 | |||
|- | |||
|0 | |||
|1 | |||
| colspan="3" |← ''r'' → | |||
|1 | |||
|1 | |||
|0 | |||
|} | |||
The 8-bit contents of the memory location HL is loaded in to register ''r'', in which ''r'' identifies any of the registers A, B, C, D, E, H or L, as follows: | |||
{{Table alignment}} | {{Table alignment}} | ||
{| class="wikitable defaultcenter" | {| class="wikitable defaultcenter" |
Revision as of 02:26, 6 November 2023
The Zilog Z80 instruction set is a simple set of instructions. There are several extensions which provides an extended set of instructions, some of which are only available on the Z180 and newer or may be undocumented instructions introduced by other manufacturers than Zilog.
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | nop | ld bc,nn | ld (bc),a | inc bc | inc b | dec b | ld b,n | rlca | ex af,af' | add hl,bc | ld a,(bc) | dec bc | inc c | dec c | ld c,n | rrca |
1 | djnz d | ld de,nn | ld (de),a | inc de | inc d | dec d | ld d,n | rla | jr d | add hl,de | ld a,(de) | dec de | inc e | dec e | ld e,n | rra |
2 | jr nz,d | ld hl,nn | ld (nn),hl | inc hl | inc h | dec h | ld h,n | daa | jr z,d | add hl,hl | ld hl,(nn) | dec hl | inc l | dec l | ld l,n | cpl |
3 | jr nc,d | ld sp,nn | ld (nn),a | inc sp | inc (hl) | dec (hl) | ld (hl),n | scf | jr c,d | add hl,sp | ld a,(nn) | dec sp | inc a | dec a | ld a,n | ccf |
4 | ld b,b | ld b,c | ld b,d | ld b,e | ld b,h | ld b,l | ld b,(hl) | ld b,a | ld c,b | ld c,c | ld c,d | ld c,e | ld c,h | ld c,l | ld c,(hl) | ld c,a |
5 | ld d,b | ld d,c | ld d,d | ld d,e | ld d,h | ld d,l | ld d,(hl) | ld d,a | ld e,b | ld e,c | ld e,d | ld e,e | ld e,h | ld e,l | ld e,(hl) | ld e,a |
6 | ld h,b | ld h,c | ld h,d | ld h,e | ld h,h | ld h,l | ld h,(hl) | ld h,a | ld l,b | ld l,c | ld l,d | ld l,e | ld l,h | ld l,l | ld l,(hl) | ld l,a |
7 | ld (hl),b | ld (hl),c | ld (hl),d | ld (hl),e | ld (hl),h | ld (hl),l | halt | ld (hl),a | ld a,b | ld a,c | ld a,d | ld a,e | ld a,h | ld a,l | ld a,(hl) | ld a,a |
8 | add a,b | add a,c | add a,d | add a,e | add a,h | add a,l | add a,(hl) | add a,a | adc a,b | adc a,c | adc a,d | adc a,e | adc a,h | adc a,l | adc a,(hl) | adc a,a |
9 | sub b | sub c | sub d | sub e | sub h | sub l | sub (hl) | sub a | sbc a,b | sbc a,c | sbc a,d | sbc a,e | sbc a,h | sbc a,l | sbc a,(hl) | sbc a,a |
A | and b | and c | and d | and e | and h | and l | and (hl) | and a | xor b | xor c | xor d | xor e | xor h | xor l | xor (hl) | xor a |
B | or b | or c | or d | or e | or h | or l | or (hl) | or a | cp b | cp c | cp d | cp e | cp h | cp l | cp (hl) | cp a |
C | ret nz | pop bc | jp nz,nn | jp nn | call nz,nn | push bc | add a,n | rst 00h | ret z | ret | jp z,nn | call z,nn | call nn | adc a,n | rst 08h | |
D | ret nc | pop de | jp nc,nn | out (n),a | call nc,nn | push de | sub n | rst 10h | ret c | exx | jp c,nn | in a,(n) | call c,nn | sbc a,n | rst 18h | |
E | ret po | pop hl | jp po,nn | ex (sp),hl | call po,nn | push hl | and n | rst 20h | ret pe | jp (hl) | jp pe,nn | ex de,hl | call pe,nn | xor n | rst 28h | |
F | ret p | pop af | jp p,nn | di | call p,nn | push af | or n | rst 30h | ret m | ld sp,hl | jp m,nn | ei | call m,nn | cp n | rst 38h |
Instructions
Instruction Notations
8-bit Load Instructions
LD r, r'
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|
0 | 1 | ← r → | ← r' → |
The contents of any register r' is loaded to any other register r. r, r' identifies any of the registers A, B, C, D, E, H or L, as follows:
A | B | C | D | E | H | L |
---|---|---|---|---|---|---|
111 | 000 | 001 | 010 | 011 | 100 | 101 |
Flags affected
None.
LD r, n
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|
0 | 0 | ← r → | 1 | 1 | 0 | ||
← n → |
The 8-bit integer n is loaded in to any register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:
A | B | C | D | E | H | L |
---|---|---|---|---|---|---|
111 | 000 | 001 | 010 | 011 | 100 | 101 |
Flags affected
None.
LD r, (HL)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|
0 | 1 | ← r → | 1 | 1 | 0 |
The 8-bit contents of the memory location HL is loaded in to register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:
A | B | C | D | E | H | L |
---|---|---|---|---|---|---|
111 | 000 | 001 | 010 | 011 | 100 | 101 |
Flags affected
None.