Logic gate: Difference between revisions
(Created page with "A '''logic gate''' is an idealized or physical device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. = Symbols = {{Table alignment}} {| class="wikitable defaultcenter" |+ !Type !ANSI symbol !Boolean algebra !Truth table |- ! colspan="4" |Single-input gates |- |Buffer |File:Buffer ANSI.svg |<math>A</math> | |- |Inverter |File:Inverter ANSI.svg |<math>\overline A</math>...") |
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A '''logic gate''' is an idealized or physical device that performs a [[Boolean function]], a logical operation performed on one or more binary inputs that produces a single binary output. | A '''logic gate''' is an idealized or physical device that performs a [[Boolean function]], a logical operation performed on one or more binary inputs that produces a single binary output. | ||
Logic gates can be constructed out of a wide range of materials, utilizing a variety of physical principles, such as pneumatic logic, fluid logic, optics, electromechanical logic such as mechanical elements and relay logic, and vacuum tubes. Primarily, modern logic gates are constructed of [[Diode|diodes]] and [[Transistor|transistors]], but more specifically [[MOSFET|MOSFETs]]. | |||
Advanced logic circuits include devices such as [[Multiplexer|multiplexers]], [[Register|registers]], [[Arithmetic Logic Unit|arithmetic logic unit]] (ALUs), and computer memory, all the way up to [[Microprocessor|microprocessors]] which may contain millions (if not billions or trillions) of logic gates. | |||
Compound logic gates such as [[AND-OR-Invert gate|AND-OR-Invert gates]] and [[OR-AND-Invert gate|OR-AND-Invert gates]] are often employed in circuit design because their construction using MOSFETs is simpler and more efficient than the sum of the individual gates. | |||
= Symbols = | = Symbols = | ||
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|<math>A</math> | |<math>A</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
|'''Input''' || '''Output''' | |||
|- style="background:#def;" | |||
| A || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{yes2|1}} | |||
|} | |||
|- | |- | ||
|[[Inverter]] | |[[Inverter]] | ||
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|<math>\overline A</math> or <math>\neg A</math> | |<math>\overline A</math> or <math>\neg A</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def; text-align:center;" | |||
| '''Input''' || '''Output''' | |||
|- style="background:#def; text-align:center;" | |||
| A || Q | |||
|- | |||
| {{no2|0}} || {{yes2|1}} | |||
|- | |- | ||
| | | {{yes2|1}} || {{no2|0}} | ||
| | |} | ||
| | |||
| | |||
|- | |- | ||
|[[AND gate]] | |[[AND gate]] | ||
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|<math>A \cdot B</math> or <math>A \land B</math> | |<math>A \cdot B</math> or <math>A \land B</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input''' || '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{no2|0}} | |||
|- " | |||
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}} | |||
|} | |||
|- | |- | ||
|[[OR gate]] | |[[OR gate]] | ||
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|<math>A + B</math> or <math>A \lor B</math> | |<math>A + B</math> or <math>A \lor B</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input'''|| '''Output''' | |||
|- style="background:#def" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{yes2|1}} | |||
|- | |- | ||
| | | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} | ||
| | |} | ||
| | |||
| | |||
|- | |- | ||
|[[NAND gate]] | |[[NAND gate]] | ||
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|<math>\overline { A \cdot B }</math> or <math>\neg(A \land B)</math> | |<math>\overline { A \cdot B }</math> or <math>\neg(A \land B)</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input'''|| '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{yes2|1}} || {{no2|0}} | |||
|} | |||
|- | |- | ||
|[[NOR gate]] | |[[NOR gate]] | ||
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|<math>\overline { A + B }</math> or <math>\neg(A \lor B)</math> | |<math>\overline { A + B }</math> or <math>\neg(A \lor B)</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input''' || '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{no2|0}} | |||
|- | |- | ||
| | | {{yes2|1}} || {{yes2|1}} || {{no2|0}} | ||
| | |} | ||
| | |||
| | |||
|- | |- | ||
|[[XOR gate]] | |[[XOR gate]] | ||
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|<math>A \oplus B</math> or <math>A \underline \lor B</math> | |<math>A \oplus B</math> or <math>A \underline \lor B</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input'''|| '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{yes2|1}} || {{yes2|1}} || {{no2|0}} | |||
|} | |||
|- | |- | ||
|[[XNOR gate]] | |[[XNOR gate]] | ||
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|<math>\overline { A \oplus B }</math> or <math>A \odot B</math> | |<math>\overline { A \oplus B }</math> or <math>A \odot B</math> | ||
| | | | ||
{{Table alignment}} | |||
{| class="wikitable defaultcenter" | |||
|- style="background:#def;" | |||
| colspan="2" |'''Input'''|| '''Output''' | |||
|- style="background:#def;" | |||
| A || B || Q | |||
|- | |||
| {{no2|0}} || {{no2|0}} || {{yes2|1}} | |||
|- | |||
| {{no2|0}} || {{yes2|1}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{no2|0}} || {{no2|0}} | |||
|- | |||
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}} | |||
|} | |||
|} | |} | ||
{{Stub}} | |||
= Tri-state Logic Gates = | |||
A tri-state logic gate is a type of logic gate that can have three different output levels: LOW (L), HIGH (H) and High-Impedance (Z). This high-impedance state plays no role in the logic, which is strictly binary. These devices are used in [[Bus (Computing)|busses]] and other digital circuits where there may be contention for one or many individual circuits. If more than one logic gate is outputting to the same circuit, damage may result if one gate is sourcing current from the positive rail and another is sinking current to the negative rail as this would result in a short circuit. If more than one logic gate were to both source or sink current and output to the same circuit, damage could result by the input of another device on that circuit sourcing or sinking more current than it is designed to. The high-impedance state of a tri-state logic device effectively "disconnects" the gate output from the circuit, allowing more than one gate to operate on the circuit, so long as it is designed that only one gate can operate at a time.{{Stub}} | |||
= See also = | |||
* [[Combinational logic]] | |||
* [[List of 4000 series integrated circuits]] | |||
* [[List of 7400 series integrated circuits]] | |||
* [[Logic level]] | |||
{{Digital systems}} | |||
[[Category:Logic gates]] | [[Category:Logic gates]] |
Latest revision as of 15:36, 9 November 2023
A logic gate is an idealized or physical device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output.
Logic gates can be constructed out of a wide range of materials, utilizing a variety of physical principles, such as pneumatic logic, fluid logic, optics, electromechanical logic such as mechanical elements and relay logic, and vacuum tubes. Primarily, modern logic gates are constructed of diodes and transistors, but more specifically MOSFETs.
Advanced logic circuits include devices such as multiplexers, registers, arithmetic logic unit (ALUs), and computer memory, all the way up to microprocessors which may contain millions (if not billions or trillions) of logic gates.
Compound logic gates such as AND-OR-Invert gates and OR-AND-Invert gates are often employed in circuit design because their construction using MOSFETs is simpler and more efficient than the sum of the individual gates.
Symbols
Type | ANSI symbol | Boolean algebra | Truth table | ||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Single-input gates | |||||||||||||||||||||
Buffer | ![]() |
| |||||||||||||||||||
Inverter | ![]() |
or |
| ||||||||||||||||||
AND gate | ![]() |
or |
| ||||||||||||||||||
OR gate | ![]() |
or |
| ||||||||||||||||||
NAND gate | ![]() |
or |
| ||||||||||||||||||
NOR gate | ![]() |
or |
| ||||||||||||||||||
XOR gate | ![]() |
or |
| ||||||||||||||||||
XNOR gate | ![]() |
or |
|
Tri-state Logic Gates
A tri-state logic gate is a type of logic gate that can have three different output levels: LOW (L), HIGH (H) and High-Impedance (Z). This high-impedance state plays no role in the logic, which is strictly binary. These devices are used in busses and other digital circuits where there may be contention for one or many individual circuits. If more than one logic gate is outputting to the same circuit, damage may result if one gate is sourcing current from the positive rail and another is sinking current to the negative rail as this would result in a short circuit. If more than one logic gate were to both source or sink current and output to the same circuit, damage could result by the input of another device on that circuit sourcing or sinking more current than it is designed to. The high-impedance state of a tri-state logic device effectively "disconnects" the gate output from the circuit, allowing more than one gate to operate on the circuit, so long as it is designed that only one gate can operate at a time.